igbt and method of making the same

专利摘要:
IGBT AND METHOD OF MANUFACTURING THE SAME. The present invention relates to an IGBT having an emitting region, an upper body region formed below the emitting region, a fluctuation region formed below the upper body region, a lower body region formed below the floating region, an ditch, an insulating door film that covers the inner surface of the ditch and a door electrode disposed inside the ditch. When looking along the thickness direction of the semiconductor substrate in the distribution of p-type impurity concentrations within the upper body region and within the fluctuation region, which are located below the emitting region, the p-type impurity concentration decreases by one downward direction from the upper edge of the upper body region positioned below the emitting region, and a minimum value is reached at a prescribed depth within the fluctuation region.
公开号:BR112014007671B1
申请号:R112014007671-5
申请日:2011-09-28
公开日:2021-01-26
发明作者:Masaru Senoo；Kyosuke Miyagi；Tsuyoshi Nishiwaki；Jun Saito
申请人:Toyota Jidosha Kabushiki Kaisha；
IPC主号:

专利说明:

[0001] [001] The technique revealed in this specification relates to an IGBT. BACKGROUND TECHNIQUE
[0002] [002] In Japanese Patent Application Publication #No. 2010- 103326 (JP-2010-103326 A) (hereinafter referred to as Patent Document 1) an IGBT having an upper body region, a fluctuation region and a lower body region is disclosed. When fabricating this IGBT, after a ditch gate electrode is formed, p-type impurities are implanted in a manner such as to stop within a range of depths in the upper body region, n-type impurities are implanted in a manner such as to stop stop within a range of depths in the fluctuation region, and p-type impurities are implanted in a manner such as to stop within a range of depths in the lower body region. Thus, the upper body region, the fluctuation region and the lower body region are formed. SUMMARY OF THE INVENTION PROBLEM TO BE SOLVED BY THE INVENTION
[0003] [003] In a method of manufacturing Patent Document 1, the respective impurities are implanted after the pit gate electrode is formed. If impurities are thus implanted in the respective regions after the ditch port electrode is formed, it is difficult to precisely control the depth of implantation of impurities in a region in the vicinity of the ditch port electrode, because of the influence of the shape of a part of recess that exists in an upper part of the ditch port electrode. The technique of Patent Document 1 explains that the depth of implantation of impurities in the region in the vicinity of the pit gate electrode is stabilized by setting the depth of the recess to a predetermined value. In this method as well, however, the implantation depth is spread over a certain extent. The ON state voltage and the gate threshold voltage are dispersed among mass-produced IGBTs, because of this dispersion of the implantation depth.
[0004] [004] In order to prevent the depth of implantation of impurities in the vicinity of the pit gate electrode from being dispersed, it is also conceivable to form the pit gate electrode after implanting the impurities. However, in a method in which impurities are implanted directly in the respective regions, as in Patent Document 1, the respective impurities need to be implanted in a deep position by means of high energy, so that a semiconductor substrate is seriously damaged. If the pit gate electrode is formed on the semiconductor substrate thus damaged, an oxidation-induced defect (hereinafter referred to as an OSF) is caused on the semiconductor substrate, in a heat treatment to form an insulating door film. Since a leakage current is produced in the semiconductor substrate with the OSF formed therein, it is difficult to adopt this method.
[0005] [005] In this way, this specification provides a technique that can restrict an ON state voltage and a gate threshold voltage from being dispersed between mass-produced IGBT's. DEVICES TO SOLVE THE PROBLEM
[0006] [006] An IGBT that is provided by this specification is equipped with a semiconductor substrate. The IGBT has an emitting region, an upper body region, a flotation region, a lower body region, a moat, a door insulating film and a door electrode. The emitting region is an n-type region that is formed in a band such as one to be exposed to an upper face of the semiconductor substrate. The upper body region is a p-type region that is formed below the emitting region. The fluctuation region is a type n region that is formed below the upper body region and separated from the emitting region by the upper body region. The lower body region is a p-type region that is formed below the flotation region and separated from the upper body region by the flotation region. The pit is formed on the upper face of the semiconductor substrate, and penetrates the emitting region, the upper body region, the flotation region and the lower body region. The insulating door film covers an inner face of the pit. The door electrode is arranged inside the pit. When a distribution of a concentration of p-type impurities in the upper body region and in the fluctuation region, which are located below the emitting region, is seen along a thickness direction of the semiconductor substrate, the concentration of p-type impurities decreases as a downward distance increases from an upper end of the upper body region which is located below the emitting region, and assumes a local minimum value at a given depth in the fluctuation region.
[0007] [007] Incidentally, the upper body region can be formed not only below the emitting region, but also next to the emitting region. In addition, the expression "a strip such as one to be exposed to the upper face of the semiconductor substrate" mentioned above means a strip that emerges on the upper face of the semiconductor substrate in the case where the electrode and the insulating film, which are formed in the semiconductor substrate, are removed. In this way, even a region whose surface is covered with the electrode and the insulating film can fit in "a strip such as one to be exposed to the upper face of the semiconductor substrate". In addition, when describing the distribution of the concentration of impurities in the semiconductor substrate in this specification, a waveform with an amplitude that is less than 30% of the concentration of impurities is a noise resulting from a measurement error, and is not treated such as a local maximum value or a local minimum value. For example, in the case where a distribution of the concentration of p-type impurities in the upper body region and in the fluctuation region as shown in graph A of Figure 41 is obtained, a positive peak value A1 and a negative peak value A2 they are not treated as a local maximum value and a local minimum value respectively. This is because the amplitude Aw (= (A1-A2) / 2) of a waveform including values A1 and A2 is less than 30% of an average A3 of value A1 and value A2. If a small waveform like this is ignored, chart A can be considered as a chart B. In addition, a positive peak value B1 from chart B is treated as a local maximum value, and a negative peak value B2 graph B is treated as a local minimum value. This is because the amplitude Bw (= (B1-B2) / 2) of a waveform including values B1 and B2 is greater than 30% of an average B3 of value B1 and value B2. In this way, graph A shown in Figure 41 has a configuration in which "the concentration of p-type impurities decreases as the downward distance increases from the upper end of the upper body region that is located below the emitting region, and assumes the local minimum value at the depth determined in the fluctuation region ". Incidentally, Figure 41 is exemplified for the purpose of illustration, and does not limit the claims. For example, the positive peak value B1 may not exist in the lower body region.
[0008] [008] In this way, the upper body region in which the concentration of p-type impurities is distributed in such a way as to decrease as the downward distance increases can be formed when implanting p-type impurities in the vicinity of the upper face of the semiconductor substrate (within a range of depths in the emitting region) and diffuse the implanted p-type impurities. In this method, the upper body region is formed by diffusing the p-type impurities implanted in a shallow position. Therefore, even if the upper body region is formed after a ditch gate electrode (a set of the insulating door film and the ditch arranged electrode in the ditch) is formed, the distribution of the p-type impurity concentration in the upper body is hardly influenced by the shape of the pit gate electrode. In addition, in this method, the ditch port electrode can also be formed after the upper body region is formed. In this case, too, almost no OSF is produced in and around the upper body region. This is because p-type impurities are implanted in the vicinity of the upper face of the semiconductor substrate, and for this reason there is no peak of p-type impurities in the upper body region, and the upper body region is hardly damaged. In this way, this upper body region can be formed stably both before the ditch gate electrode is formed and after the ditch gate electrode is formed. The distribution of the concentration of p-type impurities in the upper body region has a great influence on the IGBT threshold limit voltage. Thus, in the case where these IGBT's are mass-produced, it is unlikely that the gate threshold voltage will be dispersed between the mass-produced IGBT's. In addition, the flotation region having a local minimum p-type impurity concentration can be realized by implanting p-type impurities in a region that is located below the flotation region (for example, the lower body region). By thus supplying the flotation region with a local minimum value of the type p impurity concentration, the difference between the type n impurity concentration and the type p impurity concentration increases, and for this reason the flotation region can be formed in a stable manner. The concentration of impurities in the fluctuation region influences the ON state voltage of the IGBT. Thus, in the case where these IGBT’s are mass produced, it is unlikely that the ON state voltage will be dispersed among the mass produced IGBT’s. In addition, p-type impurities are implanted in the region that is located below the previously mentioned flotation region with high energy. Therefore, this implantation needs to be performed after the ditch port electrode is formed. If p-type impurities are implanted in a deep position after the ditch port electrode is formed, the impurity implantation depth is unstable in the vicinity of the ditch port electrode, as previously described. In this way, it is difficult to control the concentration of impurities in the region that is located below the fluctuation region (for example, the lower body region). However, the inventors found that the distribution of the concentration of impurities in the vicinity of the ditch gate electrode located below the flotation region does not have a major influence on the characteristics of the IGBT's (the ON state voltage, the threshold port voltage and others). In this way, the characteristics of IGBT’s are hardly dispersed as a result of the dispersion of the distribution of the concentration of impurities in the region that is located below the fluctuation region. In this way, when these IGBT’s are mass produced, it is unlikely that the ON state voltage and the gate threshold voltage will be dispersed among the IGBT’s.
[0009] [009] In the aforementioned IGBT, it is preferable that when a distribution of a concentration of type n impurities in the fluctuation region is seen along the thickness direction of the semiconductor substrate, a local maximum value of the concentration of type n impurities does not exist in the fluctuation region.
[0010] [0010] This fluctuation region can be formed by implanting type n impurities in the vicinity of the upper face of the semiconductor substrate (within the depth range of the emitting region) and spreading the implanted type n impurities. Alternatively, a fluctuation region like this can also be formed by means of epitaxial growth. This method makes it possible to control the concentration of type n impurities in the flotation region without being influenced by the shape of the pit gate electrode. In this way, when these IGBT’s are mass produced, it is more unlikely that the ON state voltage will be dispersed among the IGBT’s.
[0011] [0011] In the aforementioned IGBT, it is preferable that the fluctuation region is formed by an epitaxial layer.
[0012] [0012] This configuration makes it possible to maintain the concentration of type n impurities in the region of substantially constant fluctuation. In this way, the concentration of type n impurities in the flotation region can be controlled more precisely. In this way, when these IGBTs are mass produced, it is more unlikely that the ON state voltage to be dispersed among the IGBTs.
[0013] [0013] In the aforementioned IGBT, it is preferable that when a distribution of a concentration of p-type impurities in the lower body region is seen along the thickness direction of the semiconductor substrate, a local maximum value of the concentration of p-type impurities exists in the lower body region.
[0014] [0014] In the case where the maximum local value of the concentration of type p impurities thus exists in the lower body region, when the IGBT’s are mass-produced, it is unlikely that the position of the lower end of the fluctuation region will be dispersed among the IGBT’s. In this way, when these IGBT’s are mass produced, it is more unlikely that the ON state voltage will be dispersed between the IGBT’s.
[0015] [0015] In the aforementioned IGBT, it is preferable that a width of the fluctuation region along the thickness direction of the semiconductor substrate in a position in contact with the insulating door film is greater than that in a position away from the insulating door film .
[0016] [0016] In this way, if the width of the flotation region is greater in the vicinity of the insulating door film where moving voids are likely to flow, a greater number of moving voids can be accumulated in the region that is located below the flotation region (for example, an offset region) when the IGBT is turned on. In this way, this configuration makes it possible to reduce the ON state voltage of the IGBT.
[0017] [0017] In the aforementioned IGBT, it is preferable that a lower end of the lower body region is located in a position in contact with the insulating door film than in a position far from the insulating door film.
[0018] [0018] This configuration makes it possible to reduce the feedback capacity of the IGBT.
[0019] [0019] In addition, this specification provides a new method of manufacturing an IGBT. This manufacturing method has a process of forming a type n emitting region in a band such as one to be exposed to an upper face of a semiconductor substrate, a process of forming a type n upper body region below a range of depths of the emitter region by implanting p-type impurities on the top face of the semiconductor substrate in such a way that the p-type impurities stop within the depth range of the emitting region, and diffuse the implanted p-type impurities, a process of forming a type n fluctuation region below of a range of depths in the upper body region when implanting type n impurities in the upper face of the semiconductor substrate in such a way that type n impurities stop within the depth range of the emitting region, and diffuse the implanted type impurities, a process of form a moat on the top face of the semiconductor substrate, and form a door insulating film that covers an inner face of the moat, and an electron gate squeegee that is arranged in the pit, and a process of forming a p-type lower body region below a range of depths of the fluctuation region by implanting p-type impurities on the top face of the semiconductor substrate in such a way that the p-type impurities they stop at a depth below the depth range of the flotation region, after forming the pit, the insulating door film and the door electrode. The pit is arranged in such a way as to penetrate the emitting region, the upper body region, the flotation region and the lower body region after the respective processes have been carried out.
[0020] [0020] Incidentally, the process of forming the emitting region, the process of forming the upper body region, the process of forming the flotation region and the process of forming the moat, the door insulating film and the door electrode can be executed in any sequence. In this way, the "range of depths of the emitting region" mentioned above can be the range of depths of the emitting region that has already been formed or the range of depths of the emitting region that is to be formed. By the same indication, each of "the depth range of the upper body region" and "the depth range of the fluctuation region" may be the depth range of the region that has already been formed or the depth range of the region that has already been formed. is to be formed. In addition, in this specification, the implantation of impurities in such a way that the impurities stop in the predetermined depth range means that the average stop position of the implanted impurities is in the predetermined depth range.
[0021] [0021] This method makes it possible to form the upper body region and the fluctuation region in a stable way by means of diffusion of impurities. In addition, the lower body region is formed by implanting p-type impurities in the deep position after the ditch port electrode is formed. Therefore, the lower body region can be formed without substantially raising the p-type impurities in the fluctuation region. In this way, if the IGBT’s are mass produced according to this manufacturing method, the ON state voltage and the gate threshold voltage are restricted from being dispersed between the mass produced IGBT’s.
[0022] [0022] In the aforementioned manufacturing method, it is preferable that the process of forming the upper body region and the process of forming the flotation region are carried out before the process of forming the pit, the insulating door film and the electrode of door.
[0023] [0023] According to this manufacturing method, the width of the fluctuation region in the vicinity of the insulating door film is increased when the insulating door film is formed. In this way, this manufacturing method makes it possible to manufacture an IGBT with a lower ON state voltage.
[0024] [0024] In the aforementioned manufacturing method, it is preferable that the p-type impurities are implanted in the semiconductor substrate with an upper face of the gate electrode present below the upper face of the semiconductor substrate, in the process of forming the lower body region.
[0025] [0025] This manufacturing method makes it possible to form the lower body region in such a way that the lower end of it is located lower in the position in contact with the insulating door film than in the distant position of the insulating door film. In this way, the IGBT's feedback capacity can be reduced.
[0026] [0026] In addition, this specification provides another manufacturing method. This method of making an IGBT has a process of inducing an epitaxial layer of a n-type semiconductor to grow on a top face of a base substrate, a process of forming an n-type emitting region in a band such as one to be exposed to. an upper face of the epitaxial layer, a process of forming a type n upper body region below a range of depths from the emitting region by implanting p-type impurities in the upper face of the epitaxial layer in such a way that the p-type impurities stop within the range depths of the emitting region, and diffuse the implanted p-type impurities, a process of forming a gap in the upper face of the epitaxial layer, and forming a door insulating film that covers an inner face of the gap, and a door electrode that is arranged in the pit, and a process of forming a p-type lower body region on the base substrate by implanting p-type impurities in the upper face of the epitaxial layer in such a way that the impurities type p stop at the base substrate, after forming the pit, the insulating door film and the door electrode. The type n epitaxial layer remains between the upper body region and the lower body region to form the flotation region, and the ditch is arranged in such a way as to penetrate the emitting region, the upper body region, the fluctuation and in the lower body region, after the respective processes mentioned above are executed.
[0027] [0027] This manufacturing method makes it possible to form the upper body region and the fluctuation region in a stable manner by means of epitaxial growth and diffusion of impurities. In this way, if the IGBT’s are mass produced according to this manufacturing method, the ON state voltage and the gate threshold voltage are restricted from being dispersed among the IGBT’s. In addition, in this manufacturing method, the flotation region consists of the n-type epitaxial layer. In this way, the concentration of type n impurities in the fluctuation region can be kept substantially constant. Thus, in the case where these IGBT’s are mass produced, it is more unlikely that the ON state voltage will be dispersed among the IGBT’s.
[0028] [0028] In the manufacturing method mentioned above to induce the epitaxial layer to grow, it is preferable that the process of forming the upper body region is carried out before the process of forming the pit, the insulating door film and the door electrode.
[0029] [0029] According to this manufacturing method, the width of the n-type epitaxial layer in the vicinity of the insulating door film (i.e., the fluctuation region) is increased when the insulating door film is formed. In this way, this manufacturing method makes it possible to manufacture an IGBT with a lower ON state voltage.
[0030] [0030] In the aforementioned manufacturing method to induce the epitaxial layer to grow, it is preferable that the p-type impurities are implanted in a semiconductor substrate with an upper face of the gate electrode present below an upper face of the semiconductor substrate, in the process to form the lower body region.
[0031] [0031] This manufacturing method makes it possible to form the lower body region in such a way that the lower end of it is located lower in the position in contact with the insulating door film than in the distant position of the insulating door film. In this way, the IGBT's feedback capacity can be reduced. BRIEF DESCRIPTION OF THE DRAWINGS
[0032] [0032] Figure 1 is a longitudinal sectional view of an IGBT 10 according to the first embodiment of the invention.
[0033] [0033] Figure 2 is a top view of IGBT 10 with an emitting electrode 60, the cover insulating films 46 and the insulating films between layers 47 not shown.
[0034] [0034] Figure 3 is a graph showing the distribution of concentrations of impurities in a semiconductor substrate on an A-A line in Figure 1.
[0035] [0035] Figure 4 is a graph showing the distribution of concentrations of impurities on the semiconductor substrate in a line B-B of Figure 1.
[0036] [0036] Figure 5 is a flowchart showing a method of making the IGBT 10.
[0037] [0037] Figure 6 is a longitudinal sectional view of a semiconductor substrate 100 prior to the start of the manufacturing method of Figure 5.
[0038] [0038] Figure 7 is a longitudinal sectional view of the semiconductor substrate 100 after performing step S2.
[0039] [0039] Figure 8 is a graph showing the distribution of a concentration of impurities on the semiconductor substrate 100 on a line C-C in Figure 7.
[0040] [0040] Figure 9 is a longitudinal sectional view of the semiconductor substrate 100 after the execution of step S4.
[0041] [0041] Figure 10 is a graph showing the distribution of concentrations of impurities on the semiconductor substrate 100 in a D-D line of Figure 9.
[0042] [0042] Figure 11 is a longitudinal sectional view of the semiconductor substrate 100 after performing step S6.
[0043] [0043] Figure 12 is a graph showing the distribution of concentrations of impurities in the semiconductor substrate 100 in an E-E line of Figure 11.
[0044] [0044] Figure 13 is a longitudinal sectional view of the semiconductor substrate 100 after performing step S8.
[0045] [0045] Figure 14 is a longitudinal sectional view of the semiconductor substrate 100 after performing step S10.
[0046] [0046] Figure 15 is a longitudinal sectional view of the semiconductor substrate 100 after performing step S12.
[0047] [0047] Figure 16 is an enlarged view of an upper face of a port electrode 44 in Figure 15.
[0048] [0048] Figure 17 is a longitudinal sectional view of the semiconductor substrate 100 after performing step S14.
[0049] [0049] Figure 18 is a longitudinal sectional view of the semiconductor substrate 100 after the execution of step S16.
[0050] [0050] Figure 19 is a longitudinal sectional view illustrating another method of forming a wide part of a fluctuation region 24.
[0051] [0051] Figure 20 is a longitudinal sectional view illustrating yet another method of forming the wide part of the fluctuation region 24.
[0052] [0052] Figure 21 is a longitudinal sectional view of an IGBT that has a wide part 24b.
[0053] [0053] Figure 22 is a top view of an IGBT according to a first example of modification as a view corresponding to Figure 2.
[0054] [0054] Figure 23 is a top view of an IGBT according to a second example of modification as a view corresponding to Figure 2.
[0055] [0055] Figure 24 is a graph of the distribution of concentrations of impurities in an IGBT according to a third example of modification in one place corresponding to Figure 4.
[0056] [0056] Figure 25 is a graph of the distribution of concentrations of impurities in an IGBT according to a fourth example of modification in one place corresponding to Figure 3.
[0057] [0057] Figure 26 is a graph of the distribution of concentrations of impurities in an IGBT according to a fifth example of modification in place corresponding to Figure 3.
[0058] [0058] Figure 27 is a graph of the distribution of concentrations of impurities in an IGBT according to a sixth example of modification in place corresponding to Figure 3.
[0059] [0059] Figure 28 is a graph of the distribution of concentrations of impurities in an IGBT according to a seventh example of modification in place corresponding to Figure 3.
[0060] [0060] Figure 29 is a graph of the distribution of concentrations of impurities in an IGBT according to an eighth example of modification in place corresponding to Figure 3.
[0061] [0061] Figure 30 is a graph of the distribution of concentrations of impurities in an IGBT according to a second embodiment of the invention in place corresponding to Figure 3.
[0062] [0062] Figure 31 is a flow chart showing a method of making the IGBT according to the second embodiment of the invention.
[0063] [0063] Figure 32 is a longitudinal sectional view of a semiconductor substrate 300 after performing step S32.
[0064] [0064] Figure 33 is a graph showing the distribution of a concentration of impurities on the semiconductor substrate 300 in a G-G line of Figure 32.
[0065] [0065] Figure 34 is a longitudinal sectional view of the semiconductor substrate 300 after the execution of step S34.
[0066] [0066] Figure 35 is a longitudinal sectional view of the semiconductor substrate 300 after performing step S42.
[0067] [0067] Figure 36 is a longitudinal sectional view of the semiconductor substrate 300 after performing step S44.
[0068] [0068] Figure 37 is a graph of the distribution of concentrations of impurities in the IGBT according to the eighth example of modification in one place corresponding to Figure 30.
[0069] [0069] Figure 38 is a graph of the distribution of concentrations of impurities in an IGBT according to a ninth example of modification in place corresponding to Figure 30.
[0070] [0070] Figure 39 is a graph of the distribution of concentrations of impurities in an IGBT according to a tenth example of modification in place corresponding to Figure 30.
[0071] [0071] Figure 40 is a graph of the distribution of concentrations of impurities in an IGBT according to an eleventh example of modification in place corresponding to Figure 30.
[0072] [0072] Figure 41 is a graph illustrating local maximum values and local minimum values in the distribution of concentrations of impurities. MODES FOR CARRYING OUT THE INVENTION FIRST MODE
[0073] [0073] The IGBT 10 shown in Figure 1 consists of a semiconductor substrate 12, and electrodes, insulating films and others that are formed on an upper face and on a lower face of the semiconductor substrate 12.
[0074] [0074] A plurality of ditches 40 are formed on the top face of the semiconductor substrate 12. An inner face of each of the ditches 40 is covered with a corresponding insulating film of the insulating films of ports 42. Each of the electrodes of gate 44 is formed inside a corresponding pit of the ditches 40. An upper face of each of the door electrodes 44 is covered with a corresponding insulating film of the cover insulating films 46. In addition, each of the insulating films between layers 47 is formed on a corresponding insulating film of cover insulating films 46. However, port electrodes 44 can be connected to the outside in positions that are not shown in the drawing. Next, the insulating films of doors 42 and the door electrodes 44 which are formed in the ditches 40 respectively will be referred to comprehensively as the ditch door electrodes 48 in some cases. As shown in Figure 2, the respective pit port electrodes 48 extend parallel to each other.
[0075] [0075] The emitting regions 20, the upper body regions 22, the fluctuation regions 24, the lower body regions 26, a displacement region 28, a separator region 30 and a collecting region 32 are formed within the semiconductor substrate 12 .
[0076] [0076] The emitting regions 20 are n-type regions, and they are selectively formed in a band such as to be exposed to an upper face of the semiconductor substrate 12. The emitting regions 20 are in contact with the insulating films of ports 42 respectively. As shown in Figure 2, the emitting regions 20 extend parallel to each other along the pit gate electrodes 48 respectively.
[0077] [0077] The upper body regions 22 are p-type regions, and are formed below the emitting regions 20 and next to the emitting regions 20 respectively. As shown in Figures 1 and 2, each of the upper body regions 22 is exposed to the upper face of the semiconductor substrate 12, between two corresponding emitting regions of the two emitting regions 20. In addition, the upper body regions 22 are in contact with the insulating films of doors 42 below the emitting regions 20 respectively.
[0078] [0078] The fluctuation regions 24 are n-type regions, and are formed below the upper body regions 22 respectively. The fluctuation regions 24 are separated from the emitter regions 20 by the upper body regions 22 respectively. The fluctuation regions 24 are in contact with the insulating films of doors 42 respectively. Upper edges of the flotation regions 24 are shifted upward as the distances to the insulating films of doors 42 decrease respectively. Lower edges of the flotation regions 24 are shifted downward as the distances to the insulating films of doors 42 decrease respectively. In this way, the widths of the fluctuation regions 24 along the thickness direction of the semiconductor substrate 12 change depending on their positions. That is, a width W1 of the floating regions 24 in positions in contact with the insulating films of doors 42 is greater than a width W2 of the floating regions 24 in positions distant from the insulating films of doors 42. These sections of the floating regions 24 having width W1 will hereinafter be referred to as wide parts 24a.
[0079] [0079] The lower body regions 26 are p-type regions, and are formed below the fluctuation regions 24 respectively. The lower body regions 26 are separated from the upper body regions 22 by the fluctuation regions 24 respectively. The lower body regions 26 are in contact with the insulating films of doors 42 respectively. Lower edges of the lower body regions 26 are located lower in positions in contact with the insulating films of doors 42 than in positions distant from the insulating films of doors 42, respectively. That is, the displacement portions 26a which are displaced downwardly through the insulating films of doors 42 respectively are formed in those sections of the lower body regions 26 which are in contact with the insulating films of doors 42 respectively.
[0080] [0080] Displacement region 28 is a type n region that contains a low concentration of type n impurities. The displacement region 28 is formed below the lower body regions 26. The displacement region 28 is separated from the fluctuation regions 24 by the lower body regions 26 respectively. The displacement region 28 is in contact with the insulating films of doors 42 which are located at the lower ends of the pits 40 respectively.
[0081] [0081] Separator region 30 is a type n region that contains a concentration of type n impurities greater than that of displacement region 28. Separator region 30 is formed below displacement region 28.
[0082] [0082] The collecting region 32 is a p-type region that contains a high concentration of p-type impurities. The collecting region 32 is formed in a strip such as one to be exposed to a lower face of the semiconductor substrate 12. The collecting region 32 is separated from the lower body regions 26 by the displacement region 28 and the separating region 30.
[0083] [0083] The respective regions are formed within the semiconductor substrate 12 as previously described. Therefore, each of the pits 40 is arranged in such a way as to penetrate a corresponding region of the emitting regions 20, a corresponding region of the upper body regions 22, a corresponding region of the fluctuation regions 24 and a corresponding region of the lower body regions 26, and to reach the displacement region 28. In addition, each of the port electrodes 44 is opposite a corresponding region of the emitting regions 20, a corresponding region of the upper body regions 22, a corresponding region of the fluctuation regions 24 and a corresponding region of the lower body regions 26, by means of a corresponding insulating film of the insulating films of doors 42 on a side face of a corresponding ditch of the ditches 40.
[0084] [0084] An emitter electrode 60 is formed on the top face of the semiconductor substrate 12. Emitter electrode 60 is connected in an ohmic manner to the emitting regions 20 and the upper body regions 22. Emitter electrode 60 is isolated from the port electrodes 44 by the insulating cover films 46 and by the insulating films between layers 47 respectively. A collector electrode 62 is formed on the underside of the semiconductor substrate 12. Collector electrode 62 is connected in an ohmic manner to the collector region 32.
[0085] [0085] Figure 3 shows the distribution of concentrations of type n impurities and type p impurities on the semiconductor substrate 12 when seen along a line AA of Figure 1. Figure 4 shows the distribution of concentrations of type n impurities and type p impurities in the semiconductor substrate 12 when viewed along a BB line in Figure 1. Incidentally, in each of Figures 3 and 4 and in the other drawings showing the distribution of concentrations of impurities (except in Figure 41), a graph that is free of forms noise wave at a lower level of measurement error is shown. In addition, each of these drawings employs a logarithmic axis as an axis representing concentration.
[0086] [0086] As shown in Figure 3, the concentration of p-type impurities assumes a maximum value at the upper ends of the emitting regions 20. The concentration of p-type impurities decreases as the downward distance increases from the upper ends of the regions stations 20, and assumes a local minimum value PLL in fluctuation regions 24. The concentration of p-type impurities increases as the downward distance increases from positions of the local minimum value PLL, and assumes a local maximum value PLH in regions lower body 26. The concentration of p-type impurities decreases as the downward distance increases from positions of the local maximum value PLH, and becomes approximately zero at edges between the lower body regions 26 and the displacement 28.
[0087] [0087] The concentration of type n impurities assumes a maximum value at the upper ends of the emitting regions 20. The concentration of type n impurities decreases as the downward distance increases from the upper ends of the emitting regions 20. The rate of decrease in the concentration of type n impurities it becomes smooth at positions 22c in the upper body regions 22. However, in regions below positions 22c, the concentration of type n impurities also decreases as the downward distance increases. The concentration of type n impurities decreases to an NL value in the lower body regions 26. In the displacement region 28, the concentration of type n impurities is substantially constant, that is, it substantially assumes the NL value.
[0088] [0088] Furthermore, as shown in Figure 4, in a line B-B equally, the concentration of type p impurities is distributed in substantially the same way as that of the concentration of type p impurities in line A-A. In addition, in the BB line, the concentration of type n impurities is less than the concentration of type p impurities in a range of depths of the emitting regions 20. Also in the line BB, below the depth range of the emitting regions 20, the concentration of Type n impurities are distributed in substantially the same manner as the concentration of type n impurities in line AA.
[0089] [0089] The following will describe a method of making the IGBT 10. The IGBT 10 is manufactured according to a flow chart shown in Figure 5. The IGBT 10 is manufactured from a semiconductor substrate 100 shown in Figure 6. The semiconductor substrate 100 is a type n silicon substrate having an NL concentration of type n impurities that is approximately equal to that of displacement region 28 (about 1x1014 cm3 in this embodiment of the invention). The thickness of the semiconductor substrate 100 is approximately 700 µm.
[0090] [0090] In step S2, as shown in Figure 7, the fluctuation regions 24 are formed on the semiconductor substrate 100. Specifically, first of all, n-type impurities (phosphorus in this embodiment of the invention) are implanted by ions on one face top of the semiconductor substrate 100. In this case, the ion acceleration energy is set to 30 keV to 300 keV, and the amount of doses is set to 1x1011 to 1x1014 / cm2. The implantation of type n impurities is carried out in such a way that the implanted type n impurities stop in a region in the vicinity of the upper face of the semiconductor substrate 100 (in a range of depths in which the emitting regions 20 are to be formed later). More specifically, the implantation of type n impurities is carried out in such a way that the average stop position of the implanted type n impurities is located in the region close to the upper face of the semiconductor substrate 100 (in the depth range in which the emitting regions 20 must be formed later). Subsequently, the semiconductor substrate 100 is subjected to a heat treatment. In this case, the semiconductor substrate 100 is kept under an atmosphere of nitrogen (N2) or oxygen (O2) at a temperature of 900 ° C to 1,250 ° C, for 30 to 120 minutes. Incidentally, the atmosphere for heat treatment can be a mixed atmosphere of nitrogen and oxygen, or an atmosphere that is obtained by adding hydrogen (H2) to oxygen, nitrogen or a mixture of these. When performing the heat treatment, the n-type impurities implanted in the semiconductor substrate 100 are diffused and activated. Thus, as shown in Figure 7, the fluctuation regions 24 are formed on the semiconductor substrate 100. As shown in Figure 8, in the fluctuation regions 24, the concentration of type n impurities is higher at a position on the upper face of the semiconductor substrate 100, and the concentration of impurities decreases as the downward distance increases from the position. The concentration of n-type impurities is thus distributed because n-type impurities are implanted in such a way as to stop in the vicinity of the upper face of the semiconductor substrate 100 and the n-type impurities are diffused.
[0091] [0091] In step S4, as shown in Figure 9, the upper body regions 22 are formed on the semiconductor substrate 100. Specifically, before anything else, p-type impurities (boron in this embodiment of the invention) are implanted by ions on the face top of the semiconductor substrate 100. In this case, the ion acceleration energy is set to 30 keV to 150 keV, and the number of doses is set to 1x1011 to 5x1014 / cm2. The implantation of p-type impurities is carried out in such a way that the implanted p-type impurities stop in the region in the vicinity of the upper face of the semiconductor substrate 100 (in the range of depths in which the emitting regions 20 are to be formed later). More specifically, the implantation of p-type impurities is carried out in such a way that the average stop position of the implanted p-type impurities is located in the region close to the upper face of the semiconductor substrate 100 (in the depth range in which the emitting regions 20 must be be formed later). Subsequently, the semiconductor substrate 100 is subjected to a heat treatment. In this case, the semiconductor substrate 100 is kept under the atmosphere of nitrogen, oxygen, a mixture of nitrogen and oxygen, or a gas that is obtained by adding hydrogen to them at a temperature of 900 ° C to 1,250 ° C, for 30 to 120 minutes. When performing the heat treatment, the p-type impurities implanted in the semiconductor substrate 100 are diffused and activated. Thus, as shown in Figure 9, the upper body regions 22 are formed within the semiconductor substrate 100. As shown in Figure 10, the concentration of p-type impurities in the semiconductor substrate 100 is highest at a position on the upper face of the semiconductor substrate 100, and decreases as the downward distance increases from the position. The concentration of p-type impurities is distributed as well because p-type impurities are implanted in such a way as to stop in the vicinity of the upper face of the semiconductor substrate 100 and the p-type impurities are diffused.
[0092] [0092] In step S6, as shown in Figure 11, the emitting regions 20 are formed on the semiconductor substrate 100. Specifically, before anything else, a protective coating is formed on the upper face of the semiconductor substrate 100. The protective coating is formed in a manner such as to cover a strip where the emitting regions 20 are not formed (a strip where the upper body regions 22 are exposed to the upper face of the semiconductor substrate 100 in Figure 11). Subsequently, n-type impurities (arsenic in this embodiment of the invention) are implanted by ions on the upper face of the semiconductor substrate 100. In this case, the ion acceleration energy is set to 30 keV to 150 keV, and the number of doses is established for 1x1013 to 1x1016 / cm2. Thus, type n impurities are implanted on the upper face of the semiconductor substrate 100 in a strip that is not covered with the protective coating. In addition, the implantation of type n impurities is carried out in such a way that the implanted type n impurities stop in the region near the upper face of the semiconductor substrate 100. Subsequently, the semiconductor substrate 100 is subjected to a heat treatment. In this case, the semiconductor substrate 100 is kept under the atmosphere of nitrogen, oxygen, a mixture of nitrogen and oxygen, or a gas that is obtained by adding hydrogen to them at a temperature of 900 ° C to 1,250 ° C, for 20 to 120 minutes. When performing the heat treatment, the n-type impurities implanted in the semiconductor substrate 100 are diffused and activated. Thus, as shown in Figure 11, the emitting regions 20 are formed. As shown in Figure 12, the concentration of n-type impurities in the emitting regions 20 is highest at the position of the top face of the semiconductor substrate 100, and decreases as the downward distance increases from the position. The concentration of n-type impurities is distributed as well because n-type impurities are implanted in such a way as to stop in the vicinity of the upper face of the semiconductor substrate 100 and the n-type impurities are diffused.
[0093] [0093] In step S8, as shown in Figure 13, ditches 40 are formed on the top face of the semiconductor substrate 100. Specifically, first of all, a recording mask is formed on the top face of the semiconductor substrate 100. Parts of aperture are formed on the recording mask in regions where pits 40 are to be formed, respectively. Subsequently, the top face of the semiconductor substrate 100 in the opening parts is etched by means of anisotropic corrosion such as RIE or the like. Thus, the pits 40 are formed on the top face of the semiconductor substrate 100. The pits 40 are formed in such a way as to reach a depth equivalent to that of the displacement region 28 of Figure 1. The recording mask is removed after recording.
[0094] [0094] In step S10, the semiconductor substrate 100 is subjected to a heat treatment at 800 ° C to 1,150 ° C in an oxidizing atmosphere. Thus, as shown in Figure 14, an oxidation film is formed on the surface of the semiconductor substrate 100. At this time, oxidation films are also formed on the inner faces of the pits 40, respectively. The oxidation films that are formed on the inner faces of the pits 40 respectively are the insulating films of doors 42. During the development of the oxidation films (the insulating films of ports 42) on the internal faces of the pits 40, the oxidation films in development absorb p-type impurities from ambient regions, and discharge n-type impurities to ambient regions from within themselves. This phenomenon is generally referred to as segregation. Because of this segregation, if the door insulating films 42 are formed, the width of the fluctuation regions 24 in the vicinity of the door insulating films 42 (the width along the thickness direction of the semiconductor substrate 100) is enlarged as shown in As a result, the wide parts 24a of the flotation regions 24 are formed in bands such as to be in contact with the insulating films of doors 42, respectively.
[0095] [0095] In step S12, polysilicon is induced to develop on the surface of the semiconductor substrate 100. Thus, the interiors of the pits 40 are loaded with polysilicon. Subsequently, the polysilicon formed on the upper face of the semiconductor substrate 100 is removed by means of corrosion. As a result, the semiconductor substrate 100 assumes a state shown in Figure 15. As shown in Figure 15, gate electrodes 44 are formed by the polysilicon remaining within the ditches 40. Incidentally, as shown in Figure 16, step S12 is performed in such a way that the upper faces of the gate electrodes 44 are located below the upper face of the semiconductor substrate 100. That is, after the execution of step S12, the shoulders H1 are formed between the door electrodes 44 and the upper face of the semiconductor substrate 100 respectively. In step S13, the semiconductor substrate 100 is subjected to heat treatment in an oxidizing atmosphere. Thus, the upper faces of the door electrodes 44 are oxidized to form the insulating cover films 46 respectively. In this case, the insulating cover films 46 with a thickness of about 30 nm are formed.
[0096] [0097] In step S14, with the intention of forming the lower body regions 26, p-type impurities are implanted in the semiconductor substrate 100. Specifically, before anything else, p-type impurities (boron in this embodiment of the invention) are implanted by ions on the upper face of the semiconductor substrate 100. In this case, the ion acceleration energy is set to 300 keV at 3 MeV, and the number of doses is set to 1x1011 to 1x1014 / cm2. This implantation of p-type impurities is carried out in such a way that the implanted p-type impurities stop in regions located below the fluctuation regions 24 (in a range of depths in which the lower body regions 26 must be formed). More specifically, this implantation of p-type impurities is carried out in such a way that the average stop position of the implanted p-type impurities is in the regions located below the fluctuation regions 24 (in the depth range in which the lower body regions 26 must be formed).
[0097] [0098] In step S15, the insulating films between layers 47 are formed on the semiconductor substrate 100 by means of CVD. In this case, insulating films between layers 47 with a thickness of about 1,000 nm are formed.,
[0098] [0096] In step S16, the lower body regions 26 are formed. Specifically, the semiconductor substrate 100 is subjected to a heat treatment by means of reflux. In this heat treatment, the semiconductor substrate 100 is retained in the nitrogen atmosphere (i.e., in a non-oxidative atmosphere) at a temperature of 900 ° C to 1000 ° C, for 15 to 60 minutes. When performing the heat treatment, the p-type impurities implanted in the semiconductor substrate 100 are diffused and activated. Thus, as shown in Figure 17, the lower body regions 26 are formed on the semiconductor substrate 100. Incidentally, since this heat treatment is carried out in the non-oxidative atmosphere, an OSF is prevented from being produced on the semiconductor substrate 100. In addition Furthermore, the type n region below the lower body regions 26 is the displacement region 28. If step S14 is performed, the distribution of the concentrations of impurities in the semiconductor substrate 100 along an FF line of Figure 17 becomes the distribution shown in Figure 3. The maximum local value PLH of the concentration of p-type impurities is formed in the lower body regions 26 because of the ion implantation of step S14 being performed in such a way that the p-type impurities stop in the bands where the regions lower body shapes 26 must be formed. In addition, since the concentration of p-type impurities in the lower body regions 26 thus becomes high, the local minimum PLL value of the p-type impurity concentration is formed in the fluctuation regions 24.
[0099] [0097] Incidentally, as previously described, during implantation of p-type impurities in step S14, the H1 shoulders are formed between the upper faces of the port electrodes 44 and the upper face of the semiconductor substrate 100 respectively. Thus, because of the influence of the shape of the H1 bosses, the mean stop position of p-type impurities is located lower in the regions close to the pit gate electrodes 48 than in the regions away from the pit gate electrodes 48, respectively . Thus, the displacement parts 26a are formed in the lower body regions 26 in bands such as to be in contact with the insulating films of doors 42, respectively.
[0100] [0098] In step S17, the insulating films covering the emitting regions 20 and the upper body regions 22 respectively are removed. Subsequently, as shown in Figure 18, the emitting electrode 60 is formed on the upper face of the semiconductor substrate 100.
[0101] [0099] In step S18, the bottom face of the semiconductor substrate 100 is worked. Specifically, first of all, the bottom face of the semiconductor substrate 100 is polished to fine tune the semiconductor substrate 100. Subsequently, the separating region 30 and the collecting region 32 are formed within the semiconductor substrate 100 by subjecting the bottom face of the semiconductor substrate 100. ion implantation and heat treatment. After that, the collector electrode 62 is formed on the underside of the semiconductor substrate 100. If step S18 is performed, IGBT 10 shown in Figure 1 will be complete.
[0102] [00100] The operation of IGBT 10 will be described below. If a voltage equal to or greater than a threshold threshold voltage (a minimum required gate voltage to connect IGBT 10) is applied to gate electrodes 44 with a voltage applied between the emitting electrode 60 and the collecting electrode 62 in such a way that the voltage of the collecting electrode 62 assumes a positive value, the IGBT 10 will be switched on. That is, channels are formed through the upper body regions 22 and the lower body regions 26 in bands such as to be in contact with the insulating films of ports 42 respectively, and electrons flow from the emitting regions 20 to the collecting region 32 through of the channels respectively. At the same time, moving voids flow from the collecting region 32 to the displacement region 28. Because of the moving voids flowing to the displacement region 28, a conductivity modulation phenomenon occurs in the displacement region 28, and the electrical resistance of the offset region 28 falls. In this way, electrons flow in the displacement region 28 with low loss. In addition, the moving voids that have flowed to the displacement region 28 flow from the displacement region 28 to the upper body regions 22. However, the fluctuation regions 24 exist between the displacement region 28 and the upper body regions 22 respectively, and these flotation regions 24 serve as barriers, thus restricting the moving voids to move towards the upper body regions 22 respectively. Thus, the concentration of moving voids in the displacement region 28 becomes high, and the electrical resistance of the displacement region 28 is further reduced. Thus, the ON state voltage of the IGBT 10 is reduced.
[0103] [00101] In addition, in the aforementioned manufacturing method, the upper body regions 22 are formed by diffusing the p-type impurities implanted in the vicinity of the upper face of the semiconductor substrate 100. As a result, in the upper body regions 22, the concentration of p-type impurities decreases as the downward distance increases or as the upward distance decreases. According to this method, the upper body regions 22 can be formed without producing a defect such as an OSF or the like in the semiconductor substrate 100 or without being influenced by the shape of the pit gate electrodes 48. That is, the positions of the upper body regions 22 and the concentration of p-type impurities in upper body regions 22 can be controlled exactly. Thus, if the IGBT’s 10 according to the first embodiment of the invention are mass-produced, it is unlikely that the gate threshold voltage will be dispersed among the mass-produced IGBT’s 10.
[0104] [00102] In addition, in the aforementioned manufacturing method, the lower body regions 26 are formed by directly implanting p-type impurities into the depth of the lower body regions 26 after forming the pit gate electrodes 48. Thus, the regions of pits lower body 26 can be formed with the concentration of p-type impurities in the regions of fluctuation 24 hardly difficult. As a result, the local minimum PLL values of the p-type impurity concentration are formed in the flotation regions 24. For this reason, the difference between the n-type impurity concentration and the p-type impurity concentration is relatively large in the flotation regions 24. Thus , the fluctuation regions 24 are likely to be formed in a stable manner. Thus, if the IGBT’s 10 according to the first embodiment of the invention are mass produced, it is unlikely that the ON state voltage will be dispersed among the mass produced IGBT’s 10.
[0105] [00103] Furthermore, if p-type impurities are implanted in the depth of the lower body regions 26 after thus forming the pit door electrodes 48, the p-type impurity implantation depth in the vicinity of the pit door electrodes 48 changes according to the shape of the H1 bosses in the upper parts of the pit door electrodes 48. Thus, the depth of implantation of p-type impurities in the vicinity of the pit door electrodes 48 cannot be controlled very exactly. However, the concentration of p-type impurities in the lower body regions 26 in the vicinity of the pit gate electrodes 48 has a small influence on the ON state voltage and on the IGBT 10 door limit voltage. Thus, the ON state voltage and the threshold limit voltage are unlikely to be dispersed because of this influence.
[0106] [00104] Furthermore, if the lower body regions 26 are formed in this way, the displacement parts 26a can be formed in the lower body regions 26 respectively. Thus, the advantages indicated below are obtained. In IGBT 10, a quantity of L1 protrusion from the pit port electrodes 48 projecting below the lower body regions 26 respectively is relatively large. Thus, the moving voids that are present in the displacement region 28 in the vicinity of the lower body regions 26 are blocked by the electrodes of projecting pit doors 48 respectively, and are restricted from displacing laterally in the displacement region 28. For this reason, a a large number of moving voids are accumulated in the displacement region 28 in the vicinity of the lower body regions 26. Thus, the ON state voltage of the IGBT 10 is reduced. On the other hand, in general, if the amount of protrusion of the pit door electrodes is increased, the contact areas between the insulating door films and the displacement region increase respectively, and the IGBT feedback capacity increases. However, in the aforementioned IGBT 10, the contact areas between the insulating films of doors 42 and the displacement region 28 are small respectively, because of the formation of the displacement parts 26a. In this way, this IGBT 10 has a small feedback capacity despite the large amount of L1 protrusion. In this way, the switching loss caused at IGBT 10 according to the first embodiment of the invention is small.
[0107] [00105] In addition, many of the moving voids that move from displacement region 28 to upper body regions 22 travel through buoyancy regions 24 in the vicinity of the insulating films of doors 42 (i.e., in the vicinity of the channels) respectively. In the aforementioned IGBT 10, the wide parts 24a of the fluctuation regions 24 are formed in the vicinity of the insulating films of doors 42 respectively. The wide parts 24a restrict the movable voids to move from the displacement region 28 to the upper body regions 22 respectively. Thus, the ON state voltage of the IGBT 10 is further reduced.
[0108] [00106] Incidentally, in the first embodiment mentioned above of the invention, the fluctuation regions 24, the upper body regions 22 and the emitting regions 20 are formed in this sequence, but the sequence in which these regions are formed can be changed in any way . Furthermore, in the case where there is no need to form the wide parts 24a in the flotation regions 24 respectively, the flotation regions 24, the upper body regions 22 and the emitting regions 20 can be formed after forming the pit gate electrodes 48. Incidentally, in the case where the emitting regions 20 are formed before forming the pit gate electrodes 48, it is preferable that arsenic is used as n-type impurities to form the emitting regions 20 as described above. This is because it is unlikely that arsenic will be thermally diffused, and for this reason it can be retained in target regions even when receiving heat when pit electrodes 48 are formed. In order to form the emitting regions 20, phosphorus can also be used instead of arsenic. In this case, it is likely that phosphorus will be thermally diffused. Therefore, it is better to form the emitting regions 20 after forming the pit gate electrodes 48. In addition, although phosphorus is used as n-type impurities to form the flotation regions 24 in the first previously mentioned embodiment of the invention, arsenic can be used in instead of phosphorus.
[0109] [00107] Furthermore, in the first previously mentioned embodiment of the invention, the wide parts 24a are formed in the flotation regions 24 respectively, by forming the insulating films of doors 42 after forming the flotation regions 24 and the upper body regions 22. However, the wide parts can be formed in the fluctuation regions 24 respectively according to the following method. In this method, before anything else, steps S2 to 4 mentioned above are performed. Subsequently, as shown in Figure 19, a mask 102 that is provided with opening parts in regions where the ditches 40 are formed respectively is formed on the top face of the semiconductor substrate 100. Then, n-type impurities are implanted in the flotation regions 24 through mask 102, and the implanted type n impurities are diffused and activated. Thus, as shown in Figure 20, the wide parts 24b are formed. Thereafter the pit gate electrodes 48 are formed in such a way as to penetrate the wide parts 24b respectively, and other necessary processes are performed to complete an IGBT shown in Figure 21.
[0110] [00108] Furthermore, in the first embodiment mentioned above of the invention, the pit gate electrodes 48, the emitting regions 20 and the upper body regions 22 are arranged as shown in Figure 2 on the upper face of the semiconductor substrate. However, these regions can be arranged as shown in Figure 22 or Figure 23.
[0111] [00109] Incidentally, in the first embodiment of the invention, the fluctuation regions 24 are formed in such a way that the concentration of type n impurities is maximized at the upper end of the semiconductor substrate 100 as shown in Figure 8. Therefore, in Figure 4 ( the distribution of concentrations of impurities in the BB line of Figure 1) likewise, the concentration of type n impurities is maximized at the upper end of semiconductor substrate 100. However, if the aforementioned middle stop position of type n impurities becomes slightly deeper than in the first embodiment of the invention, the concentration of impurities in the BB line is as shown in Figure 24. That is, a local maximum value NLH of the concentration of impurities type n is formed within the depth range of the emitting regions 20 Thus, even if the maximum local value NLH of the concentration of type n impurities is formed within the depth range of the emitting regions 20, no problem is caused in particular as long as there is no local maximum value for the concentration of type n impurities in the upper body regions 22 and in the fluctuation regions 24 which are located below the emitting regions 20 respectively. This is because the depth of implantation of type n impurities is shallow and for this reason no problem such as an OSF or the like is not caused within the depth range of the emitting regions 20. By the same indication, as shown in Figure 25, a local maximum value PLH2 of the concentration of p-type impurities can be within the depth range of the emitting regions 20.
[0112] [00110] In addition, as shown in Figure 26, a local maximum value NLH2 of the concentration of type n impurities can be in the emitting regions 20. In addition, as shown in Figure 27, the local minimum value of the concentration of impurities PLL type p can be greater than the NL concentration of type n impurities in the displacement region 28. In addition, Figure 28 represents the distribution of concentrations of the impurities implanted in steps S2, S4, S6 and S14, separately for each of the steps. As shown in Figure 28, part of the p-type impurities implanted in step S14 can be distributed in the emitting regions 20. For example, as shown in Figure 28, the concentration of n-type impurities at a crossing point C1 of a graph of the concentration of type p impurities implanted in step S14 and a graph of the concentration of type n impurities implanted in step S6 can be greater than the NL concentration of type n impurities in displacement region 28 (the concentration of type n impurities in the original semiconductor substrate 100 ).
[0113] [00111] Furthermore, as shown in Figure 29, part of the n-type impurities implanted and spread in step S2 can be distributed to a region below the lower body regions 26. That is, a region 28a in which the concentration of impurities type n is greater than the NL concentration can be formed below the lower body regions 26. In this configuration, the displacement region 28 is formed by a total n type region that includes the region 28a and is located below the lower body regions. This structure can be formed by extending the diffusion distance of the type n impurities implanted in step S2. By thus extending the diffusion distance of type n impurities, the gradient of the distribution of the concentration of type n impurities in the fluctuation regions 24 becomes small, and the distribution of the concentration of type n impurities becomes almost flat. For this reason, the fluctuation regions 24 can be formed stably, and the dispersion of the ON state voltage is further reduced. In addition, by thus extending the diffusion distance of type n impurities, the concentration of type n impurities in the upper body regions 22 becomes low, and the dispersion of the threshold threshold voltage is further reduced. SECOND MODE
[0114] [00112] In the following, an IGBT according to the second embodiment of the invention will be described. The respective parts are arranged in the IGBT according to the second embodiment of the invention in substantially the same way as in IGBT 10 according to the first embodiment of the invention shown in Figures 1 and 2. However, the IGBT according to the second embodiment of the invention it is different from IGBT 10 according to the first modality of the invention in the distribution of the concentrations of impurities. As shown in Figure 30, in the IGBT according to the second embodiment of the invention, the concentration of n-type impurities is substantially constant in the upper body regions 22 and in the fluctuation regions 24.
[0115] [00113] In the following, a method of making the IGBT according to the second embodiment of the invention will be described. The IGBT according to the second embodiment of the invention is manufactured according to a flow chart of Figure 31. The IGBT according to the second embodiment of the invention is manufactured from a silicon substrate (hereinafter referred to as a base substrate) that has substantially the same NL concentration of n-type impurities as in the displacement region 28.
[0116] [00114] In step S32, as shown in Figure 32, a type n semiconductor layer 210 in which the concentration of type n impurities is greater than in a base 200 substrate is induced to grow epitaxially on the base substrate 200. The type n semiconductor layers 210 will now be referred to as an epitaxial layer 210. In addition, the epitaxial layer 210 and the base substrate 200 will be referred to comprehensively as a semiconductor substrate 300. If step S32 is performed, the concentration of impurities in the semiconductor substrate 300 is distributed as shown in Figure 33. As shown in the drawing, the concentration of n-type impurities in the epitaxial layer 210 is substantially constant.
[0117] [00115] In step S34, as shown in Figure 34, the upper body regions 22 are formed in the epitaxial layer 210. In this case, p-type impurities are implanted by ions in an upper face of the epitaxial layer 210 under a condition similar to that from step S4 mentioned earlier. That is, p-type impurities are implanted in such a way that the average stop position of the implanted p-type impurities is in a region close to the upper face of the epitaxial layer 210 (within a range of depths where the emitting regions 20 are to be formed later). Subsequently, the semiconductor substrate 300 is heat treated under a condition similar to that of step S4 mentioned above, and the implanted p-type impurities are diffused and activated. Thus, the upper body regions 22 are formed in the epitaxial layer 210. In this case, the upper body regions 22 are formed in such a way that the type n epitaxial layer 210 remains below the upper body regions 22. The type n epitaxial layer 210 which is located below each of the upper body regions 22 turns out to be a corresponding region of the fluctuation regions 24.
[0118] [00116] In step S36, the emitting regions 20 are formed in the epitaxial layer 210 in the same way as in step S6 mentioned above. In step S38, the ditches 40 that penetrate the emitting regions 20, the upper body regions 22 and the flotation regions 24 to reach the base substrate 200 are formed on an upper face of the semiconductor substrate 300. In step S40, the films door insulators 42 are formed in the same way as in step S10 mentioned above. At this time, the wide parts 24a are formed in the fluctuation regions 24 in the vicinity of the insulating films of doors 42, respectively. In step S42, gate electrodes 44 are formed in the same way as in step S12 mentioned above. After step S42 is performed, the semiconductor substrate 300 assumes a state shown in Figure 35.
[0119] [00117] In step S44, as shown in Figure 36, the lower body regions 26 are formed in those regions on the base substrate 200 that are in contact with the fluctuation regions 24 respectively. In step S44, p-type impurities are implanted in such a way that the average stop position of the implanted p-type impurities is located in the regions below the fluctuation regions 24 (within the depth range of the lower body regions 26 that must be formed) under a condition similar to that of step S14 mentioned above. Subsequently, the semiconductor substrate 300 undergoes heat treatment, and p-type impurities are diffused and activated. Thus, as shown in Figure 36, the lower body regions 26 are formed. Incidentally, the displacement parts 26a are formed in the lower body regions 26 respectively because of the influence of the projections between the upper faces of the port electrodes 44 and the upper face of the epitaxial layer 210.
[0120] [00122] Steps S45, 46 and 48 are performed in the same way as steps S15, 16 and S18 respectively. Thus, an IGBT that has a cross sectional structure shown in Figure 1 and the distribution of concentrations of impurities shown in Figure 30 is complete.
[0121] [00123] In the IGBT according to the second modality of the invention, the advantages indicated below are obtained in addition to the advantages obtained by IGBT 10 according to the first modality of the invention. In the IGBT according to the second embodiment of the invention, the flotation regions 24 are formed from the type n epitaxial layer 210. In the case where the fluctuation regions 24 are thus formed by means of epitaxial growth, the concentration of type n impurities in the regions of flotation 24 can be made larger than in the case where the flotation regions 24 are formed by means of diffusion as in the first embodiment of the invention. Thus, the fluctuation regions 24 can be formed in a more stable manner, and the dispersion of the ON state voltage between the IGBT's can be further reduced when the IGBT's are mass produced.
[0122] [00118] Furthermore, in the IGBT according to the second embodiment of the invention, as shown in Figure 30, the concentration of type n impurities in the fluctuation regions 24 is substantially constant. In this way, the dispersion of the ON state voltage is also reduced. That is, in IGBT 10 according to the first embodiment of the invention, as shown in Figure 3, a maximum NFH value for the concentration of type n impurities in the fluctuation regions 24 exists at edges between the upper body regions 22 and the regions of fluctuation 24 respectively. If the concentration of p-type impurities in the vicinity of the edges changes, the maximum NFH value also changes. The maximum NFH value has an influence on the IGBT ON state voltage. Thus, in IGBT 10 according to the first modality of the invention, the concentration of p-type impurities in the vicinity of the edges constitutes a factor that determines the ON state voltage of IGBT 10. On the other hand, in IGBT according to the second modality of the invention, the concentration of n-type impurities in the fluctuation regions 24 is substantially constant. Therefore, even if the concentration of type p impurities in the vicinity of the edges changes, the maximum value of the concentration of type n impurities in the fluctuation regions 24 does not change. In this way, in the IGBT according to the second embodiment of the invention, the number of factors determining the ON state voltage is reduced. Therefore, it is more unlikely that the ON state voltage will be dispersed among the IGBT’s when the IGBT’s are mass produced.
[0123] [00119] Incidentally, in the second embodiment of the invention, the local maximum PLH value of the concentration of type p impurities is in the lower body regions 26. However, as shown in Figure 37, the local maximum PLH value can exist at the edges between the flotation regions 24 and lower body regions 26 respectively, or, as shown in Figure 38, the local maximum PLH value can exist in the floating regions 24. Furthermore, in the second embodiment of the invention, the local maximum PLH value is less than the concentration of type n impurities in the fluctuation regions 24. However, as shown in Figure 39, the maximum local value PLH can be approximately equal to the concentration of type n impurities in the regions of fluctuation 24, or, as shown in Figure 40, the local maximum PLH value can be greater than the concentration of type n impurities in the fluctuation regions 24. In addition, in the IGBT according to the second embodiment of the invention, the concentrations of impurities are also can also be distributed as previously described for Figures 24 to 28.
[0124] [00120] Furthermore, in the IGBT according to the second embodiment of the invention, the respective regions can also be arranged as shown in Figures 22 and 23.
[0125] [00121] Furthermore, although the IGBT that is formed on the semiconductor substrate has been described in each of the first embodiment of the invention and the second embodiment of the invention, another semiconductor element can be further formed on the semiconductor substrate. For example, in addition to the IGBT, a diode whose electrical conduction direction is contrary to that of the IGBT can be formed on the semiconductor substrate.
[0126] [00122] Furthermore, although the heat treatment to diffuse impurities to the upper body regions and the heat treatment to diffuse impurities to the flotation regions are carried out individually in each of the first embodiment of the invention and the second embodiment of the invention, the diffusion of impurities to the fluctuation regions and the diffusion of impurities to the upper body regions can be carried out by means of a single heat treatment.
[0127] [00123] The modalities of the invention have been described above in detail. However, these embodiments of the invention are nothing more than exemplifications, and do not limit the claims. The technique exposed in the claims encompasses several modifications and changes to the concrete examples shown above
[0128] [00124] The technical elements illustrated in this specification or in the drawings show technical utility alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing the order. In addition, the technique exemplified in this specification or in the drawings achieves a plurality of objectives at the same time, and is technically useful in achieving one of these objectives themselves.

权利要求:
Claims (12)
[0001]
IGBT (10) which is equipped with a semiconductor substrate (12), the IGBT (10) characterized by comprising: a type n emitting region (20) which is formed in a strip such as one to be exposed to an upper face of the semiconductor substrate (12); a p-type upper body region (22) that is formed below the emitting region (20); a type n fluctuation region (24) that is formed below the upper body region (22) and separated from the emitting region (20) by the upper body region (22); a p-type lower body region (26) that is formed below the flotation region (24) and separated from the upper body region (22) by the flotation region (24); a ditch (40) that is formed on the upper face of the semiconductor substrate (12) and penetrates the emitting region (20), the upper body region (22), the flotation region (24) and the lower body region (26 ); an insulating door film (46) covering an inner face of the pit (40); and a gate electrode (44) which is arranged inside the pit (40), in which, when a distribution of a concentration of p-type impurities in the upper body region (22) and in the fluctuation region (24), which are located below the emitting region (20), is seen along a direction of substrate thickness semiconductor (12), the concentration of p-type impurities decreases as a downward distance increases from an upper end of the upper body region (22) which is located below the emitting region (20), and assumes a minimum value location at a given depth in the flotation region (24). when a distribution of a concentration of p-type impurities in the fluctuation region (24) is seen along the thickness direction of the semiconductor substrate (12), in a region below the first predetermined depth, the concentration of p-type impurities increases with the downward distance increases between the first predetermined depth and a lower end of the fluctuation region (24), or increases as the downward distance increases from the first predetermined depth, assumes a local minimum value at a second predetermined depth and decreases with downward distance increases from the second predetermined depth.
[0002]
IGBT (10) according to claim 1, characterized by the fact that, when a distribution of a concentration of type n impurities in the fluctuation region (24) is seen along the thickness direction of the semiconductor substrate (12), a local maximum value of the concentration of type n impurities does not exist in the fluctuation region (24 ).
[0003]
IGBT (10) according to claim 1 or 2, characterized by the fact that the fluctuation region (24) is formed by an epitaxial layer (210).
[0004]
IGBT (10) according to any one of claims 1 to 3, characterized by the fact that, when a distribution of a concentration of type p impurities in the lower body region (26) and the fluctuation region is seen along the thickness direction of the semiconductor substrate (12), the concentration of type p impurities increases with the distance down it increases between the first predetermined depth and the lower end of the fluctuation region and a local maximum value for the concentration of type p impurities exists in the lower body region (26).
[0005]
IGBT (10) according to any one of claims 1 to 4, characterized by the fact that a width of the fluctuation region (24) along the thickness direction of the semiconductor substrate (12) is greater in a position in contact with the insulating door film (46) than in a distant position of the insulating door film (46 ).
[0006]
IGBT (10) according to any one of claims 1 to 5, characterized by the fact that a lower end of the lower body region (26) is located lower in a position in contact with the insulating door film (46) than in a distant position from the insulating door film (46).
[0007]
Method of making an IGBT (10), characterized by comprising: a process (S6) of forming an emitting region type n (20) in a strip such as one to be exposed to an upper face of a semiconductor substrate (12); a process (S4) of forming a p-type upper body region (22) below a depth range of the emitting region (20) by implanting p-type impurities in the upper face of the semiconductor substrate (12) in such a way that the impurities type p stop within the depth range of the emitting region (20), and spread the implanted p-type impurities; a process (S2) of forming a type n fluctuation region (24) below a range of depths in the upper body region (22) by implanting type n impurities in the upper face of the semiconductor substrate (12) in such a way that the impurities type n stop within the depth range of the emitting region (20), and diffuse type n implanted impurities; a process (S8, S10, S12) of forming a gap (40) on the top face of the semiconductor substrate (12), and forming a door insulation film (42) that covers an inner face of the gap (40), and a door electrode (44) which is arranged in the pit (40); and a process (S16) of forming a p-type lower body region (26) below a depth range of the flotation region (24) by implanting p-type impurities in the upper face of the semiconductor substrate (12) in such a way that the impurities type p stop at a depth below the depth range of the flotation region (24), after forming the gap (40), the door insulating film (42) and the door electrode (44), where the pit (40) is arranged in such a way as to penetrate the emitting region (20), the upper body region (22), the flotation region (24) and the lower body region (26) after the respective processes to be executed.
[0008]
Manufacturing method according to claim 7, characterized by the fact that the process (S4) of forming the upper body region (22) and the process (S2) of forming the flotation region (24) are carried out before the process (S8, S10, S12) of forming the gap (40), the door insulating film (42) and the door electrode (44).
[0009]
Manufacturing method according to claim 7 or 8, characterized by the fact that P-type impurities are implanted in the semiconductor substrate (12) with an upper face of the gate electrode (44) present below the upper face of the semiconductor substrate (12), in the process (S16) of forming the lower body region (26) .
[0010]
Method of making an IGBT (10), characterized by comprising: a process (S32) of inducing an epitaxial layer (100) of a n-type semiconductor to grow on an upper face of a base substrate (200); a process (S36) of forming an emitting region type n (20) in a band such as one to be exposed to an upper face of the epitaxial layer (100); a process (S34) of forming a p-type upper body region (22) below a depth range of the emitting region (20) by implanting p-type impurities in the upper face of the epitaxial layer (100) in such a way that the type impurities p stop within the depth range of the emitting region (20), and spread the implanted p-type impurities; a process (S38, S40, S42) of forming a gap (40) on the top face of the epitaxial layer (100), and forming a door insulating film (42) that covers an inner face of the gap (40), and an electrode door (44) which is arranged in the pit (40); and a process (S44) of forming a p-type lower body region (26) on the base substrate (200) by implanting p-type impurities in the upper face of the epitaxial layer (100) in such a way that the p-type impurities stop on the substrate of base (200), after forming the gap (40), the door insulating film (42) and the door electrode (44), in which the n-type epitaxial layer (100) remains between the upper body region (22) and the lower body region (26) to constitute the flotation region (24), and the moat (40) is arranged in a manner such as to penetrate the emitting region (20), the upper body region (22), the flotation region (24) and the lower body region (26), after the respective processes are executed.
[0011]
Manufacturing method according to claim 10, characterized by the fact that the process (S34) of forming the upper body region (22) is carried out before the process (S38, S40, S42) of forming the pit (40), the insulating door film (42) and the door electrode (44 ).
[0012]
Manufacturing method according to claim 10 or 11, characterized by the fact that p-type impurities are implanted in a semiconductor substrate (12) with an upper face of the gate electrode (44) present below an upper face of the semiconductor substrate (12), in the process (S44) of forming the lower body region ( 26).

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法律状态:
2018-12-26| B06F| Objections, documents and/or translations needed after an examination request according art. 34 industrial property law|

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2019-11-26| B06U| Preliminary requirement: requests with searches performed by other patent offices: suspension of the patent application procedure|

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2020-12-01| B09A| Decision: intention to grant|

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2021-01-26| B16A| Patent or certificate of addition of invention granted|Free format text: PRAZO DE VALIDADE: 20 (VINTE) ANOS CONTADOS A PARTIR DE 28/09/2011, OBSERVADAS AS CONDICOES LEGAIS. |

优先权:

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申请号 | 申请日 | 专利标题

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PCT/JP2011/072274|WO2013046378A1|2011-09-28|2011-09-28|Igbt and manufacturing method therefor|

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